This invention relates to transistor devices and fabrication methods therefor, and more particularly to field effect transistors and fabrication methods therefor.
Field effect transistors (FET) have become the dominant active device for very large scale integration (VLSI) and ultra large scale integration (ULSI) applications, such as logic devices, memory devices and microprocessors, because the integrated circuit FET is by nature a high impedance, high density, low power device. Much research and development activity has focused on improving the speed and integration density of FETs, and on lowering the power consumption thereof. FETs also are widely used as power devices, such as power amplifiers. Much research and development activity has focused on improving the speed and efficiency of FETs that are used as power devices, particularly at high frequencies, for wired and wireless applications.
A high speed, high performance field effect transistor is described in U.S. Pat. Nos. 4,984,043 and 4,990,974, both by Albert W. Vinal, both entitled Fermi Threshold Field Effect Transistor and both assigned to the assignee of the present invention. These patents describe a metal oxide semiconductor field effect transistor (MOSFET) which operates in the enhancement mode without requiring inversion, by setting the device""s threshold voltage to twice the Fermi potential of the semiconductor material. As is well known to those having skill in the art, Fermi potential is defined as that potential for which an energy state in a semiconductor material has a probability of one-half of being occupied by an electron. As described in the above mentioned Vinal patents, when the threshold voltage is set to twice the Fermi potential, the dependence of the threshold voltage on oxide thickness, channel length, drain voltage and substrate doping is substantially eliminated. Moreover, when the threshold voltage is set to twice the Fermi potential, the vertical electric field at the substrate face between the oxide and channel is minimized, and is in fact substantially zero. Carrier mobility in the channel is thereby maximized, leading to a high speed device with greatly reduced hot electron effects.
Notwithstanding the vast improvement of the Fermi-threshold FET compared to known FET devices, there was a need to lower the capacitance of the Fermi-FET device. Accordingly, in U.S. Pat. Nos. 5,194,923 and 5,369,295, both by Albert W. Vinal, and both entitled Fermi Threshold Field Effect Transistor With Reduced Gate and Diffusion Capacitance, a Fermi-FET device is described which allows conduction carriers to flow within the channel at a predetermined depth in the substrate below the gate, without requiring an inversion layer to be created at the surface of the semiconductor in order to support carrier conduction. Accordingly, the average depth of the channel charge requires inclusion of the permittivity of the substrate as part of the gate capacitance. Gate capacitance is thereby substantially reduced.
As described in the aforesaid ""295 and ""923 patents, the low capacitance Fermi-FET is preferably implemented using a Fermi-tub region having a predetermined depth and a conductivity type opposite the substrate and the same conductivity type as the drain and source. The Fermi-tub extends downward from the substrate surface by a predetermined depth, and the drain and source diffusions are formed in the Fermi-tub within the tub boundaries. The Fermi-tub forms a unijunction transistor, in which the source, drain, channel and Fermi-tub are all doped the same conductivity type, but at different doping concentrations. A low capacitance Fermi-FET is thereby provided. The low capacitance Fermi-FET including the Fermi-tub will be referred to herein as a xe2x80x9clow capacitance Fermi-FETxe2x80x9d or a xe2x80x9cTub-FETxe2x80x9d.
Notwithstanding the vast improvement of the Fermi-FET and the low capacitance Fermi-FET compared to known FET devices, there was a continuing need to increase the current per unit channel width which is produced by the Fermi-FET. As is well known to those skilled in the art, higher current Fermi-FET devices will allow greater integration density, and/or much higher speeds for logic devices, memory devices, microprocessors and other integrated circuit devices. Accordingly, U.S. Pat. No. 5,374,836 to Albert W. Vinal and the present inventor Michael W. Dennen entitled High Current Fermi-Threshold Field Effect Transistor, describes a Fermi-FET which includes an injector region of the same conductivity type as the Fermi-tub region and the source region, adjacent the source region and facing the drain region. The injector region is preferably doped at a doping level which is intermediate to the relatively low doping concentration of the Fermi-tub and the relatively high doping concentration of the source. The injector region controls the depth of the carriers injected into the channel and enhances injection of carriers in the channel, at a predetermined depth below the gate. Transistors according to U.S. Pat. No. 5,374,836 will be referred to herein as a xe2x80x9chigh current Fermi-FETxe2x80x9d.
Preferably, the source injector region is a source injector tub region which surrounds the source region. A drain injector tub region may also be provided. A gate sidewall spacer which extends from adjacent the source injector region to adjacent the gate electrode of the Fermi-FET may also be provided in order to lower the pinch-off voltage and increase saturation current for the Fermi-FET. A bottom leakage control region of the same conductivity type as the substrate may also be provided.
Notwithstanding the vast improvement of the Fermi-FET, the low capacitance Fermi-FET and the high current Fermi-FET compared to known FET devices, there was a continuing need to improve operation of the Fermi-FET at low voltages. As is well known to those having skill in the art, there is currently much emphasis on low power portable and/or battery-powered devices which typically operate at power supply voltages of five volts, three volts, one volt or less.
For a given channel length, lowering of the operating voltage causes the lateral electric field to drop linearly. At very low operating voltages, the lateral electric field is so low that the carriers in the channel are prevented from reaching saturation velocity. This results in a precipitous drop in the available drain current. The drop in drain current effectively limits the decrease in operating voltage for obtaining usable circuit speeds for a given channel length.
In order to improve operation of the Tub-FET at low voltages, U.S. Pat. No. 5,543,654 to the present inventor Michael W. Dennen entitled Contoured-Tub Fermi-Threshold Field Effect Transistor and Method of Forming Same, describes a Fermi-FET which includes a contoured Fermi-tub region having nonuniform tub depth. In particular, the Fermi-tub is deeper under the source and/or drain regions than under the channel region. Thus, the tub-substrate junction is deeper under the source and/or drain regions than under the channel region. Diffusion capacitance is thereby reduced compared to a Fermi-tub having a uniform tub depth, so that high saturation current is produced at low voltages.
In particular, a contoured-tub Fermi-threshold field effect transistor according to the ""654 patent includes a semiconductor substrate of first conductivity type and spaced-apart source and drain regions of second conductivity type in the semiconductor substrate at a face thereof. A channel region of the second conductivity type is also formed in the semiconductor substrate at the substrate face between the spaced-apart source and drain regions. A tub region of the second conductivity type is also included in the semiconductor substrate at the substrate face. The tub region extends a first predetermined depth from the substrate face to below at least one of the spaced-apart source and drain regions, and extends a second predetermined depth from the substrate face to below the channel region. The second predetermined depth is less than the first predetermined depth. A gate insulating layer and source, drain and gate contacts are also included. A substrate contact may also be included.
Preferably, the second predetermined depth, i.e. the depth of the contoured-tub adjacent the channel, is selected to satisfy the Fermi-FET criteria as defined in the aforementioned U.S. Pat. Nos. 5,194,923 and 5,369,295. In particular, the second predetermined depth is selected to produce zero static electric field perpendicular to the substrate face at the bottom of the channel with the gate electrode at ground potential. The second predetermined depth may also be selected to produce a threshold voltage for the field effect transistor which is twice the Fermi potential of the semiconductor substrate. The first predetermined depth, i.e. the depth of the contoured-tub region adjacent the source and/or drain is preferably selected to deplete the tub region under the source and/or drain regions upon application of zero bias to the source and/or drain contact.
As the state of the art in microelectronic fabrication has progressed, fabrication linewidths have been reduced to substantially less than one micron. These decreased linewidths have given rise to the xe2x80x9cshort channelxe2x80x9d FET wherein the channel length is substantially less than one micron and is generally less than one half micron with current processing technology.
The low capacitance Fermi-FET of U.S. Pat. Nos. 5,194,923 and 5,369,295, the high current Fermi-FET of U.S. Pat. No. 5,374,836 and the contoured tub Fermi-FET of U.S. Pat. No. 5,543,654 may be used to provide a short channel FET with high performance capabilities at low voltages. However, it will be recognized by those having skill in the art that as linewidths decrease, processing limitations may limit the dimensions and conductivities which are attainable in fabricating an FET. Accordingly, for decreased linewidths, processing conditions may require reoptimization of the Fermi-FET transistor to accommodate these processing limitations.
Reoptimization of the Fermi-FET transistor to accommodate processing limitations was provided in U.S. Pat. No. 5,814,869 to the present inventor Michael W. Dennen and entitled xe2x80x9cShort Channel Fermi-Threshold Field Effect Transistorsxe2x80x9d; assigned to the assignee of the present invention, the disclosure of which is hereby incorporated herein by reference. The Short Channel Fermi-FET of U.S. Pat. No. 5,814,869, referred to herein as the xe2x80x9cshort channel Fermi-FETxe2x80x9d, includes spaced-apart source and drain regions which extend beyond the Fermi-tub in the depth direction and which may also extend beyond the Fermi-tub in the lateral direction. Since the source and drain regions extend beyond the tub, a junction with the substrate is formed which can lead to a charge-sharing condition. In order to compensate for this condition, the substrate doping is increased. The very small separation between the source and drain regions leads to a desirability to reduce the tub depth. This causes a change in the static electrical field perpendicular to the substrate at the oxide:substrate interface when the gate electrode is at threshold potential. In typical long channel Fermi-FET transistors, this field is essentially zero. In short channel devices the field is significantly lower than a MOSFET transistor, but somewhat higher than a long channel Fermi-FET.
In particular, a short channel Fermi-FET includes a semiconductor substrate of first conductivity type and a tub region of second conductivity type in the substrate at a surface thereof which extends a first depth from the substrate surface. The short channel Fermi-FET also includes spaced-apart source and drain regions of the second conductivity type in the tub region. The spaced-apart source and drain regions extend from the substrate surface to beyond the first depth, and may also extend laterally away from one another to beyond the tub region.
A channel region of the second conductivity type is included in the tub region, between the spaced-apart source and drain regions and extending a second depth from the substrate surface such that the second depth is less than the first depth. At least one of the first and second depths are selected to minimize the static electric field perpendicular to the substrate surface, from the substrate surface to the second depth when the gate electrode is at threshold potential. For example, a static electric field of 104 V/cm may be produced in a short channel Fermi-FET compared to a static electric field of more than 105 V/cm in a conventional MOSFET. In contrast, the Tub-FET of U.S. Pat. Nos. 5,194,923 and 5,369,295 may produce a static electric field of less than (and often considerably less than) 103 V/cm which is essentially zero when compared to a conventional MOSFET. The first and second depths may also be selected to produce a threshold voltage for the field effect transistor which is twice the Fermi-potential of the semiconductor substrate, and may also be selected to allow carriers of the second conductivity type to flow from the source region to the drain region in the channel region at the second depth upon application of the threshold voltage to the gate electrode, and extending from the second depth toward the substrate surface upon application of voltage to the gate electrode beyond the threshold voltage of the field effect transistor, without creating an inversion layer in the channel. The transistor further includes a gate insulating layer and source, drain and gate contacts. A substrate contact may also be included.
Continued miniaturization of integrated circuit field effect transistors has reduced the channel length to well below one micron. This continued miniaturization of the transistor has often required very high substrate doping levels. High doping levels and the decreased operating voltages which may be required by the smaller devices, may cause a large increase in the capacitance associated with the source and drain regions of both the Fermi-FET and conventional MOSFET devices.
In particular, as the Fermi-FET is scaled to below one micron, it is typically necessary to make the tub depth substantially shallower due to increased Drain Induced Barrier Lowering (DIBL) at the source. Unfortunately, even with the changes described above for the short channel Fermi-FET, the short channel Fermi-FET may reach a size where the depths and doping levels which are desired to control Drain Induced Barrier Lowering and transistor leakage become difficult to manufacture. Moreover, the high doping levels in the channel may reduce carrier mobility which also may reduce the high current advantage of the Fermi-FET technology. The ever higher substrate doping levels, together with the reduced drain voltage may also cause an increase in the junction capacitance.
A short channel Fermi-FET that can overcome these potential problems was provided in application Ser. No. 5,698,884 to the present inventor Michael W. Dennen and entitled xe2x80x9cShort Channel Fermi-Threshold Field Effect Transistors Including Drain Field Termination Region and Methods of Fabricating Samexe2x80x9d assigned to the assignee of the present invention, the disclosure of which is hereby incorporated herein by reference. This Fermi-FET includes drain field terminating means between the source and drain regions for reducing and preferably preventing injection of carriers from the source region into the channel as a result of drain bias. A short channel Fermi-FET including drain field terminating means, referred to herein as a xe2x80x9cVinal-FETxe2x80x9d in memory of the now deceased inventor of the Fermi-FET, prevents excessive Drain Induced Barrier Lowering while still allowing low vertical field in the channel, similar to a Fermi-FET. In addition, the Vinal-FET permits much higher carrier mobility and simultaneously leads to a large reduction in source and drain junction capacitance.
The drain field terminating means is preferably embodied by a buried contra-doped layer between the source and drain regions and extending beneath the substrate surface from the source region to the drain region. In particular, a Vinal-FET includes a semiconductor substrate of first conductivity type and a tub region of second conductivity type in the substrate at a surface thereof. Spaced apart source and drain regions of the second conductivity type are included in the tub region at the substrate surface. A buried drain field terminating region of the first conductivity type is also included in the tub region. The buried drain field terminating region extends beneath the substrate surface from the source region to the drain region. A gate insulating layer and source, drain and gate electrodes are also included. Accordingly, the Vinal-FET may be regarded as a Fermi-FET with an added contra-doped buried drain field terminating region which prevents drain bias from causing carriers to be injected from the source region into the tub region.
As the channel length and integration density of integrated circuit field effect transistors continues to increase, the operating voltages of the transistors has also continued to decrease. This decrease is further motivated by the increasing use of integrated circuits in portable electronic devices, such as laptop computers, cellular telephones, personal digital assistants and the like. As the operating voltage of the field effect transistors decrease, it is also generally desirable to lower the threshold voltage.
Accordingly, in order to provide short channel Fermi-FETs for low voltage operation, it is desirable to reduce the threshold voltage, for example to about half a volt or less. However, this reduction in threshold voltage should not produce performance degradation in other areas of the Fermi-FET. For example, a reduction in threshold voltage should not unduly increase the leakage current of the Fermi-FET, or unduly decrease the saturation current of the Fermi-FET.
A Fermi-FET that can provide low voltage operation is described in Published PCT Application No. WO 99/17371 entitled Metal Gate Fermi-Threshold Field Effect Transistors to the present inventor Dennen and William R. Richards, assigned to the assignee of the present invention, the disclosure of which is hereby incorporated herein by reference. As described therein, a Fermi-threshold field effect transistor includes a metal gate. A contra-doped polysilicon gate is not used directly on the gate insulating layer. The metal gate can lower the threshold voltage of the Fermi-FET without degrading other desirable characteristics of the Fermi-FET. Preferably, the metal gate comprises metal having a work function between that of P-type polysilicon and N-type polysilicon. More preferably, the metal gate comprises metal having a work function of about 4.85 volts, i.e. midway between the work function of P-type polysilicon and N-type polysilicon.
As the channel length of field effect transistors continues to decrease, for example to sub-micron and sub-tenth micron dimensions, undesirable short channel effects may continue to increase. It may be desirable to produce very shallow source and drain regions in an attempt to reduce the short channel effects. However, it may become increasingly difficult to produce shallow source/drain regions, so that short channel effects may play an increasing role in reducing the performance of Fermi-threshold field effect transistors.
Embodiments of the present invention include Fermi-threshold field effect transistors (Fermi-FET) that include a trench in the tub region and an insulated gate electrode in the trench. These transistors, referred to herein as trench gate Fermi-FETs, can provide reduced short channel effects without the need for hyper-shallow source and drain profiles. High breakdown voltages and/or lower source and drain parasitic capacitances also may be provided.
Field effect transistors according to embodiments of the invention include a semiconductor substrate of first conductivity type having a surface. A tub region of second conductivity type is in the semiconductor substrate at the surface and extends into the semiconductor substrate a first depth from the first surface. Spaced apart source and drain regions of the second conductivity type are included in the tub region of second conductivity type at the surface, to define single conductivity junctions of the second conductivity type with the tub region of second conductivity type. The spaced apart source and drain regions extend into the tub region a second depth that is less than the first depth. A trench is included in the tub region, between the spaced apart source and drain regions, and extending from the surface into the tub region to a third depth that is more than the second depth but is less than the first depth. An insulated gate electrode is included in the trench. Source and drain electrodes are provided on the surface that electrically contact the source and drain regions respectively.
In some embodiments, at least one of the first, second and third depths are selected to produce zero static electric field perpendicular to the surface at the third depth. In other embodiments, at least one of the first, second and third depths are selected to produce zero static electric field perpendicular to the surface at the third depth upon application of the threshold voltage of the field effect transistor to the insulated gate electrode.
In yet other embodiments, at least one of the first, second and third depths are selected to produce the static electric field of less than 700V per centimeter, perpendicular to the surface at the third depth. In other embodiments, at least one of the first, second and third depths are selected to produce a static electric field perpendicular to the surface at the third depth that is at least an order of magnitude less than that produced by a field effect transistor that does not include the tub region. In still other embodiments, at least one of the first, second and third depths are selected to produce a static electric field perpendicular to the surface at the third depth that is less than one half of that produced by a field effect transistor that does not include the tub region. In yet other embodiments, at least one of the first, second and third depths are selected to produce a static electric field perpendicular to the surface at the third depth that is less than one fifth of that produced by a field effect transistor that does not include the tub region. In other embodiments, these static electric fields are produced perpendicular to the surface at the third depth upon application of the threshold voltage of the field effect transistor to the insulated gate electrode.
In yet other embodiments, at least one of the first, second and third depths are selected to produce a threshold voltage for the field effect transistor that is twice the Fermi potential of the semiconductor substrate.
In still other embodiments, at least one of the first, second and third depths are selected to allow carriers of the second conductivity type to flow in the tub region, beneath the trench at the third depth, upon application of the threshold voltage of the field effect transistor to the gate electrode. In still other embodiments, at least one of the first, second and third depths are selected to allow carriers of the second conductivity type to flow in the tub region, beneath the trench and extending from the third depth towards the first depth upon application of voltage to the gate electrode beyond the threshold voltage of the field effect transistor.
In yet other embodiments, the trench defines a trench width, and at least one of the first, second and third depths are selected to form a channel in the tub region beneath the trench, and having a channel length that is proportional to the trench width and that is independent of a difference between the first depth and the second depth. In yet other embodiments, at least one of the first, second and third depths are selected to deplete the tub region beneath the trench from the third depth to the first depth.
In still other embodiments, the trench includes a trench floor and the insulated gate includes an insulating layer having a thickness on the trench floor and a gate electrode on the insulating layer opposite the trench floor. At least one of the first, second and third depths are selected to produce threshold voltage for the field effect transistor that is independent of the thickness of the insulating layer on the trench floor. In still other embodiments, the trench defines a trench width and at least one of the first, second and third depths are selected to form a channel in the tub region upon application of the threshold voltage of the field effect transistor to the gate electrode, wherein the channel is confined to beneath the trench, extends across the trench width and has uniform thickness beneath the trench and across the trench width.
In still other embodiments, the third depth is less than the first depth by an amount that is equal to:                               2          ⁢                      ϵ            s                    ⁢          kT                q            ⁢              (                              N            a                                                              N                d                            ⁢                              N                a                                      +                          N              d              2                                      )            ⁢      ln      ⁢              (                                            N              d                        ⁢                          N              a                                            n            i            2                          )              ,
where Nd is the doping density of the tub region, Na is the doping density of the semiconductor substrate, Ni is the intrinsic carrier concentration of the substrate at temperature T degrees Kelvin, xcex5s is the permittivity of the substrate, q is 1.6xc3x9710xe2x88x9219 coulombs and k is 1.38xc3x9710xe2x88x9223 Joules/degree Kelvin.
The semiconductor substrate in all of the above-described embodiments may actually be a well region of first conductivity type that itself is in a semiconductor substrate of second conductivity type, at the surface, such that the tub region of second conductivity type is in the well region of first conductivity type at the surface, and extends into the well region a first depth from the surface.
Moreover, in all of the above-described embodiments, the insulated gate electrode may be in the trench and recessed beneath the surface. In some embodiments, the insulated gate electrode is recessed beneath the surface by an amount that minimizes capacitance between the insulated gate electrode and the spaced apart source and drain regions, without reducing drain current in the field effect transistor.
In still other embodiments, the semiconductor substrate is doped a first conductivity type at a first doping density and the tub region is doped the second conductivity type at a second doping density. At least one of the first, second and third depths and the first and second doping densities are selected according to any of the embodiments that are described above.
Field effect transistors may be fabricated, according to embodiments of the invention, by forming a tub region of second conductivity type in a semiconductor substrate of first conductivity type at a surface thereof, and extending into the semiconductor substrate a first depth from the surface. A source/drain region of the second conductivity type is formed in the tub region of second conductivity type at the surface, to define a single conductivity junction of the second conductivity type with the tub region of second conductivity type. The source/drain region extends into the tub region a second depth that is less than the first depth. A trench is formed in the source/drain region, to define spaced apart source and drain regions therefrom. The trench extends from the surface into the tub region a third depth that is more than the second depth but is less than the first depth. An insulated gate electrode is formed in the trench. Source and drain electrodes are formed on the surface that electrically contact the source and drain regions, respectively.
In other embodiments, the source/drain region is formed prior to forming the tub region. In yet other embodiments, the trench is formed after forming the source/drain region and forming the tub region. In still other embodiments, the insulated gate electrode is formed prior to forming the source and drain electrodes. In all of the above-described method embodiments, the first, second and third depths and/or the first and second doping densities are selected as was described in any of the structural embodiments that were described above. Moreover, a well region of first conductivity type may be formed in a semiconductor substrate of second conductivity type, and the tub region of second conductivity type may be formed in the well region of first conductivity type, as was described above. Finally, the insulated gate electrode may be recessed beneath the surface, as was described above.
In these method embodiments, the source/drain region may be formed by implanting ions of the second conductivity type into the semiconductor substrate at a large tilt angle. This can allow shallow source/drain regions to be produced, but need not cause misalignment because the gate electrode is formed after the source/drain region is produced. The gate electrode therefore may not act to shadow the source/drain implants. Moreover, the insulated gate electrode may be formed by lining the trench with an insulating layer and forming a gate electrode in the trench that is lined with the insulating layer. The gate electrode may be formed by forming a gate electrode layer on the surface and in the trench, and planarizing the gate electrode layer to remove the gate electrode layer from the surface. The planarizing may be followed by recessing the gate electrode beneath the surface.
The trench (third) depth may be determined by forming trench gate Fermi-FET field effect transistors and measuring the parameters thereof Moreover, the trench depth may be determined by simulation. Empirical methods also may be used to determine the trench depth according to embodiments of the invention, by performing a series of capacitance vs. voltage measurements on a series of sites having a tub region and a source/drain region therein, wherein the source/drain region is etched by differing amounts in the series of sites. The sites may be on a single wafer or on multiple wafers. The trench depth may be determined by determining a maximum depth that allows a maximum capacitance to be obtained at negative voltages.